 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| a FEATURES PERFORMANCE 19 ns Instruction Cycle Time from 26.32 MHz Crystal @ 3.3 Volts 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 300 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode INTEGRATION ADSP-2100 Family Code Compatible, with Instruction Set Extensions 80K Bytes of On-Chip RAM, Configured as 16K Words On-Chip Program Memory RAM 16K Words On-Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 128-Lead LQFP, 144-Ball Mini-BGA SYSTEM INTERFACE 16-Bit Internal DMA Port for High Speed Access to On-Chip Memory 4 MByte Memory Interface for Storage of Data Tables and Program Overlays 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers I/O Memory Interface with 2048 Locations Supports Parallel Peripherals Programmable Memory Strobe and Separate I/O Memory Space Permits "Glueless" System Design Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling ICE-PortTM Emulator Interface Supports Debugging in Final Systems ICE-Port is a trademark of Analog Devices, Inc. DATA ADDRESS GENERATORS DAG 1 DAG 2 PROGRAM SEQUENCER DSP Microcomputer ADSP-2183 FUNCTIONAL BLOCK DIAGRAM POWERDOWN CONTROL MEMORY PROGRAM MEMORY DATA MEMORY PROGRAMMABLE I/O FLAGS BYTE DMA CONTROLLER EXTERNAL ADDRESS BUS PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA EXTERNAL DATA BUS ARITHMETIC UNITS ALU MAC SHIFTER SERIAL PORTS SPORT 0 SPORT 1 TIMER INTERNAL DMA PORT DMA BUS ADSP-2100 BASE ARCHITECTURE GENERAL DESCRIPTION The ADSP-2183 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2183 combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The ADSP-2183 integrates 80K bytes of on-chip memory configured as 16K words (24-bit) of program RAM, and 16K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-2183 is available in 128-lead LQFP, and 144-Ball Mini-BGA packages. In addition, the ADSP-2183 supports new instructions, which include bit manipulations--bit set, bit clear, bit toggle, bit test-- new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory transfers and global interrupt masking, for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2183 operates with a 19 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-2183's flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle the ADSP-2183 can: * Generate the next program address * Fetch the next instruction * Perform one or two data moves * Update one or two data address pointers * Perform a computational operation REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000 ADSP-2183 This takes place while the processor continues to: * Receive and transmit data through the two serial ports * Receive and/or transmit data through the internal DMA port * Receive and/or transmit data through the byte DMA port * Decrement timer Development System ARCHITECTURE OVERVIEW The ADSP-2100 Family Development Software, a complete set of tools for software and hardware system development, supports the ADSP-2183. The assembler has an algebraic syntax that is easy to program and debug. The linker combines object files into an executable file. The simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different portions of the hardware environment. The EZ-KIT Lite is a hardware/software kit offering a complete development environment for the ADSP-21xx family: an ADSP-2189M evaluation board with PC monitor software plus Assembler, Linker, Simulator and PROM Splitter software. The ADSP-2189M evaluation board is a low-cost, easy to use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite include the following features: * 35.7 MHz ADSP-2189M * Full 16-bit Stereo Audio I/O with AD73322 CODEC * RS-232 Interface * EZ-ICE Connector for Emulator Control * DSP Demo Programs * Evaluation Suite of VisualDSP The ADSP-218x EZ-ICE(R) Emulator aids in the hardware debugging of ADSP-218x systems. The ADSP-218x integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection requiring fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. The ADSP-218x device need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs. The EZ-ICE performs a full range of functions, including: * In-target operation * Up to 20 breakpoints * Single-step or full-speed operation * Registers and memory values can be examined and altered * PC upload and download functions * Instruction-level emulation of program booting and execution * Complete assembly and disassembly of instructions * C source-level debugging (See Designing An EZ-ICE-Compatible Target System section of this data sheet for exact specifications of the EZ-ICE target board connector.) Additional Information This data sheet provides a general overview of ADSP-2183 functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2100 Family User's Manual, Third Edition. For more information about the development tools, refer to the ADSP-2100 Family Development Tools Data Sheet. The ADSP-2183 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-2183 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. Figure 1 is an overall block diagram of the ADSP-2183. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. The shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. The ADSP-21xx family DSPs contain a shadow register that is useful for single cycle context switching of the processor. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop counters and loop stacks, the ADSP-2183 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. Efficient data transfer is achieved with the use of five internal buses: * Program Memory Address (PMA) Bus * Program Memory Data (PMD) Bus * Data Memory Address (DMA) Bus * Data Memory Data (DMD) Bus * Result (R) Bus The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permitting the ADSP-2183 to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP-2183 can fetch an operand from program memory and the next instruction in the same cycle. EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc. -2- REV. C ADSP-2183 In addition to the address and data bus for external memory connection, the ADSP-2183 has a 16-bit Internal DMA port (IDMA port) for connection to external systems. The IDMA port is made up of 16 data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSPs on-chip program and data RAM. An interface to low cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables. The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH and BG). One execution mode (Go Mode) allows the ADSP-2183 to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted. The ADSP-2183 can respond to thirteen possible interrupts, eleven of which are accessible at any given time. There can be up to six external interrupts (one edge-sensitive, two levelsensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. The ADSP-2183 provides up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programmable as inputs or outputs and three flags are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) is decremented every n processor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). Serial Ports The ADSP-2183 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2183 SPORTs. Refer to the ADSP-2100 Family User's Manual, Third Edition, for further details. * SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section. * SPORTs can use an external serial clock or generate their own serial clock internally. * SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals, internally or externally generated. Frame sync signals are active high or inverted, with either of two pulsewidths and timings. 21xx CORE ADSP-2183 INTEGRATION POWER DOWN CONTROL LOGIC INSTRUCTION REGISTER PROGRAM SRAM 16k 24 DATA SRAM 16k 16 2 DATA ADDRESS GENERATOR #1 DATA ADDRESS GENERATOR #2 PMA BUS BYTE DMA CONTROLLER PROGRAMMABLE I/O FLAGS 8 3 PROGRAM SEQUENCER 14 PMA BUS 14 MUX EXTERNAL ADDRESS BUS DMA BUS 14 DMA BUS PMD BUS 24 PMD BUS EXTERNAL DATA BUS DMD BUS BUS EXCHANGE DMD BUS MUX 24 16 INPUT REGS INPUT REGS INPUT REGS INPUT REGS MAC MAC INPUT REGS SHIFTER COMPANDING CIRCUITRY TIMER TRANSMIT REG TRANSMIT REG RECEIVE REG SERIAL PORT 0 RECEIVE REG SERIAL PORT 0 ALU ALU INTERNAL DMA PORT 16 OUTPUT REGS OUTPUT REGS OUTPUT REGS OUTPUT REGS OUTPUT REGS 16 R BUS 4 INTERRUPTS 5 5 Figure 1. Block Diagram REV. C -3- ADSP-2183 * SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and -law companding according to CCITT recommendation G.711. * SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. * SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer. * SPORT0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time-division multiplexed, serial bitstream. * SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the Flag In and Flag Out signals. The internally generated serial clock may still be used in this configuration. Pin Descriptions Pin Name(s) # of Pins Input/ Output Function O I/O I/O I I I I/O O I O O I/O * * * * * * * * * Processor Clock Output. Serial Port I/O Pins Serial Port 1 or Two External IRQs, Flag In and Flag Out IDMA Port Read/Write Inputs IDMA Port Select IDMA Port Address Latch Enable IDMA Port Address/Data Bus IDMA Port Access Ready Acknowledge Power-Down Control Power-Down Control Output Flags Programmable I/O Pins (Emulator Only*) (Emulator Only*) (Emulator Only*) (Emulator Only*) (Emulator Only*) (Emulator Only*) (Emulator Only*) (Emulator Only*) (Emulator Only*) Ground Pins (LQFP) Power Supply Pins (LQFP) Ground Pins (Mini-BGA) Power Supply Pins (Mini-BGA) CLKOUT 1 SPORT0 5 SPORT1 5 IRD, IWR IS IAL IAD IACK PWD PWDACK FL0, FL1, FL2 PF7:0 EE EBR EBG ERESET EMS EINT ECLK ELIN ELOUT GND VDD GND VDD 2 1 1 16 1 1 1 3 8 1 1 1 1 1 1 1 1 1 11 6 22 11 The ADSP-2183 is available in a 128-lead LQFP package, and Mini-BGA. PIN FUNCTION DESCRIPTIONS Pin Name(s) Address Data # of Pins 14 24 Input/ Output Function O I/O Address Output Pins for Program, Data, Byte, & I/O Spaces Data I/O Pins for Program and Data Memory Spaces (8 MSBs Are Also Used as Byte Space Addresses) Processor Reset Input Edge- or Level-Sensitive Interrupt Request Level-Sensitive Interrupt Requests Edge-Sensitive Interrupt Request Bus Request Input Bus Grant Output Bus Grant Hung Output Program Memory Select Output Data Memory Select Output Byte Memory Select Output I/O Space Memory Select Output Combined Memory Select Output Memory Read Enable Output Memory Write Enable Output Memory Map Select Input Boot Option Control Input Clock or Quartz Crystal Input RESET IRQ2 IRQL0, IRQL1 IRQE BR BG BGH PMS DMS BMS IOMS CMS RD WR MMAP BMODE CLKIN, XTAL 1 1 I I 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 I I I O O O O O O O O O I I I *These ADSP-2183 pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors. Interrupts The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. The ADSP-2183 provides four dedicated external interrupt input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six external interrupts. The ADSP2183 also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable (except power-down and reset). The IRQ2, IRQ0 and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are levelsensitive and IRQE is edge sensitive. The priorities and vector addresses of all interrupts are shown in Table I. -4- REV. C ADSP-2183 Table I. Interrupt Priority and Interrupt Vector Addresses Power-Down Source of Interrupt Reset (or Power-Up with PUCR = 1) Power-Down (Nonmaskable) IRQ2 IRQL1 IRQL0 SPORT0 Transmit SPORT0 Receive IRQE BDMA Interrupt SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 Timer Interrupt Vector Address (Hex) 0000 (Highest Priority) 002C 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 (Lowest Priority) The ADSP-2183 processor has a low power feature that lets the processor enter a very low power dormant state through hardware or software control. Here is a brief list of powerdown features. Refer to the ADSP-2100 Family User's Manual, Third Edition, "System Interface" chapter for detailed information about the power-down feature. * Quick recovery from power-down. The processor begins executing instructions in as few as 300 CLKIN cycles. * Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during power-down without affecting the lowest power rating and 300 CLKIN cycle recovery. * Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits 4096 CLKIN cycles for the crystal oscillator to start and stabilize), and letting the oscillator run to allow 300 CLKIN cycle start-up. * Power-down is initiated by either the power-down pin (PWD) or the software power-down force bit. * Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The power-down interrupt also can be used as a nonmaskable, edge-sensitive interrupt. * Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. * The RESET pin also can be used to terminate power-down. * Power-down acknowledge pin indicates when the processor has entered power-down. Idle Interrupt routines can either be nested, with higher priority interrupts taking precedence, or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable. The ADSP-2183 masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers. The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1 and IRQ2 external interrupts to be either edge- or level-sensitive. The IRQE pin is an external edge-sensitive interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level-sensitive interrupts. The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are twelve levels deep to allow interrupt, loop and subroutine nesting. The following instructions allow global enable or disable servicing of the interrupts (including power down), regardless of the state of IMASK. Disabling the interrupts does not affect serial port autobuffering or DMA. ENA INTS; DIS INTS; When the processor is reset, interrupt servicing is enabled. LOW POWER OPERATION When the ADSP-2183 is in the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. Slow Idle The IDLE instruction is enhanced on the ADSP-2183 to let the processor's internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction. The format of the instruction is IDLE (n); where n = 16, 32, 64 or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While it is in this state, the processor's other internal clock signals, such as SCLK, CLKOUT and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction. The ADSP-2183 has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are: * Power-Down * Idle * Slow Idle The CLKOUT pin may also be disabled to reduce external power dissipation. REV. C -5- ADSP-2183 When the IDLE (n) instruction is used, it effectively slows down the processor's internal clock, and thus its response time, to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2183 will remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64 or 128) before resuming normal operation. When the IDLE (n) instruction is used in systems with an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor's reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). SYSTEM INTERFACE If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processor's CLKIN input. When an external clock is used, the XTAL input must be left unconnected. The ADSP-2183 uses an input clock with a frequency equal to half the instruction rate; a 16.67 MHz input clock yields a 30 ns processor cycle (which is equivalent to 33 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. Because the ADSP-2183 includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. A clock output (CLKOUT) signal is generated by the processor at the processor's cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register. Figure 2 shows a typical basic system configuration with the ADSP-2183, two serial devices, a byte-wide EPROM and optional external program and data overlay memories. Programmable wait state generation allows the processor to connect easily to slow peripheral devices. The ADSP-2183 also provides four external interrupts and two serial ports or six external interrupts and one serial port. ADSP-2183 CLKIN 1/2x CLOCK OR CRYSTAL CLKIN XTAL FL0-2 PF0-7 IRQ2 IRQE IRQL0 IRQL1 DATA23-0 BMS A10-0 ADDR RD WR IOMS A13-0 ADDR D23-0 DATA PMS DMS CMS BR BG BGH PWD PWDACK D23-8 DATA ADDR13-0 D23-16 24 D15-8 DATA CS A0-A21 14 A13-0 XTAL CLKOUT DSP BYTE MEMORY Figure 3. External Crystal Connections Reset SPORT1 SERIAL DEVICE SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI I/O SPACE (PERIPHERALS) 2048 LOCATIONS CS SPORT0 SERIAL DEVICE SCLK0 RFS0 TFS0 DT0 DR0 IRD IWR IS IAL IACK IAD15-0 OVERLAY MEMORY TWO 8K PM SEGMENTS TWO 8K DM SEGMENTS The RESET signal initiates a master reset of the ADSP-2183. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulsewidth specification, tRSP. The RESET input contains some hysteresis; however, if you use an RC circuit to generate your RESET signal, the use of an external Schmidt trigger is recommended. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting (MMAP = 0), the boot-loading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. IDMA PORT SYSTEM INTERFACE OR CONTROLLER 16 Figure 2. ADSP-2183 Basic System Configuration Clock Signals The ADSP-2183 can be clocked by either a crystal or a TTLcompatible clock signal. The CLKIN input cannot be halted, changed during operation or operated below the specified frequency during normal operation. The only exception is while the processor is in the powerdown state. For additional information, refer to Chapter 9, ADSP-2100 Family User's Manual, Third Edition, for detailed information on this power-down feature. -6- REV. C ADSP-2183 Memory Architecture Table II. The ADSP-2183 provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory and I/O. Program Memory is a 24-bit-wide space for storing both instruction opcodes and data. The ADSP-2183 has 16K words of Program Memory RAM on chip and the capability of accessing up to two 8K external memory overlay spaces using the external data bus. Both an instruction opcode and a data value can be read from on-chip program memory in a single cycle. Data Memory is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The ADSP-2183 has 16K words on Data Memory RAM on chip, consisting of 16,352 user-accessible locations and 32 memorymapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. Byte Memory provides access to an 8-bit-wide memory space through the Byte DMA (BDMA) port. The Byte Memory interface provides access to 4 MBytes of memory by utilizing eight data lines as additional address lines. This gives the BDMA Port an effective 22-bit address range. On power-up, the DSP can automatically load bootstrap code from byte memory. I/O Space allows access to 2048 locations of 16-bit-wide data. It is intended to be used to communicate with parallel peripheral devices such as data converters and external registers or latches. Program Memory PMOVLAY Memory 0 1 Internal External Overlay 1 External Overlay 2 A13 Not Applicable 0 A12:0 Not Applicable 13 LSBs of Address Between 0x2000 and 0x3FFF 13 LSBs of Address Between 0x2000 and 0x3FFF 2 1 This organization provides for two external 8K overlay segments using only the normal 14 address bits. This allows for simple program overlays using one of the two external segments in place of the on-chip memory. Care must be taken in using this overlay space because the processor core (i.e., the sequencer) does not take the PMOVLAY register value into account. For example, if a loop operation were occurring on one of the external overlays, and the program changes to another external overlay or internal memory, an incorrect loop operation could occur. In addition, care must be taken in interrupt service routines as the overlay registers are not automatically saved and restored on the processor mode stack. For ADSP-2100 Family compatibility, MMAP = 1 is allowed. In this mode, booting is disabled and overlay memory is disabled (PMOVLAY must be 0). Figure 5 shows the memory map in this configuration. PROGRAM MEMORY ADDRESS 0x3FFF The ADSP-2183 contains a 16K x 24 on-chip program RAM. The on-chip program memory is designed to allow up to two accesses each cycle so that all operations can complete in a single cycle. In addition, the ADSP-2183 allows the use of 8K external memory overlays. The program memory space organization is controlled by the MMAP pin and the PMOVLAY register. Normally, the ADSP2183 is configured with MMAP = 0 and program memory organized as shown in Figure 4. PROGRAM MEMORY ADDRESS 0x3FFF INTERNAL 8K (PMOVLAY = 0, MMAP = 1) 0x2000 0x1FFF 8K EXTERNAL 0x0000 Figure 5. Program Memory (MMAP = 1) Data Memory 8K INTERNAL (PMOVLAY = 0, MMAP = 0) OR EXTERNAL 8K (PMOVLAY = 1 or 2, MMAP = 0) 0x2000 0x1FFF The ADSP-2183 has 16,352 16-bit words of internal data memory. In addition, the ADSP-2183 allows the use of 8K external memory overlays. Figure 6 shows the organization of the data memory. DATA MEMORY ADDRESS 0x3FFF 8K INTERNAL 0x0000 32 MEMORY- MAPPED REGISTERS 0x3FEO 0x3FDF Figure 4. Program Memory (MMAP = 0) There are 16K words of memory accessible internally when the PMOVLAY register is set to 0. When PMOVLAY is set to something other than 0, external accesses occur at addresses 0x2000 through 0x3FFF. The external address is generated as shown in Table II. INTERNAL 8160 WORDS 0x2000 8K INTERNAL (DMOVLAY = 0) OR EXTERNAL 8K (DMOVLAY = 1, 2) 0x1FFF 0x0000 Figure 6. Data Memory REV. C -7- ADSP-2183 There are 16,352 words of memory accessible internally when the DMOVLAY register is set to 0. When DMOVLAY is set to something other than 0, external accesses occur at addresses 0x0000 through 0x1FFF. The external address is generated as shown in Table III. Table III. The CMS pin functions like the other memory select signals, with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits, except the BMS bit, default to 1 at reset. Byte Memory DMOVLAY 0 1 Memory Internal A13 Not Applicable A12:0 Not Applicable 13 LSBs of Address Between 0x0000 and 0x1FFF 13 LSBs of Address Between 0x0000 and 0x1FFF The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K x 8. The byte memory space on the ADSP-2183 supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows up to a 4 meg x 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register. Byte Memory DMA (BDMA) External 0 Overlay 1 External 1 Overlay 2 2 This organization allows for two external 8K overlays using only the normal 14 address bits. All internal accesses complete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register. I/O Space The Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space, while the processor is operating normally and steals only one DSP cycle per 8-, 16- or 24-bit word transferred. The BDMA circuit supports four different data formats which are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. Table V shows the data formats supported by the BDMA circuit. Table V. The ADSP-2183 supports an additional external memory space called I/O space. This space is designed to support simple connections to peripherals or to bus interface ASIC data registers. I/O space supports 2048 locations. The lower eleven bits of the external address bus are used; the upper 3 bits are undefined. Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated 3-bit wait state registers, IOWAIT0-3, which specify up to seven wait states to be automatically generated for each of four regions. The wait states act on address ranges as shown in Table IV. Table IV. BTYPE 00 01 10 11 Internal Memory Space Program Memory Data Memory Data Memory Data Memory Word Size 24 16 8 8 Alignment Full Word Full Word MSBs LSBs Address Range 0x000-0x1FF 0x200-0x3FF 0x400-0x5FF 0x600-0x7FF Wait State Register IOWAIT0 IOWAIT1 IOWAIT2 IOWAIT3 Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers. BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations. The source or destination of a BDMA transfer will always be on-chip program or data memory, regardless of the values of MMAP, PMOVLAY or DMOVLAY. Composite Memory Select (CMS) The ADSP-2183 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can combine their functionality. When set, each bit in the CMSSEL register causes the CMS signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory; use either DMS or PMS as the additional address bit. -8- REV. C ADSP-2183 When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses. The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor and start execution at address 0 when the BDMA accesses have completed. Internal Memory DMA Port (IDMA Port) Table VI. Boot Summary Table MMAP 0 BMODE 0 Booting Method BDMA feature is used in default mode to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to. Bootstrap features disabled. Program execution immediately starts from location 0. 0 1 1 X The IDMA Port provides an efficient means of communication between a host system and the ADSP-2183. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP's memorymapped control registers. The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written to while the ADSP-2183 is operating at full speed. The DSP memory address is latched and then automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access. IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location; the destination type specifies whether it is a DM or PM access. The falling edge of the address latch signal latches this value into the IDMAA register. Once the address is stored, data can either be read from or written to the ADSP-2183's on-chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR respectively) signals the ADSP-2183 that a particular transaction is required. In either case, there is a one-processorcycle delay for synchronization. The memory access consumes one additional processor cycle. Once an access has occurred, the latched address is automatically incremented and another access can occur. Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation. Bootstrap Loading (Booting) BDMA Booting When the BMODE and MMAP pins specify BDMA booting (MMAP = 0, BMODE = 0), the ADSP-2183 initiates a BDMA boot sequence when reset is released. The BDMA interface is set up during reset to the following defaults when BDMA booting is specified: the BDIR, BMPAGE, BIAD and BEAD registers are set to 0, the BTYPE register is set to 0 to specify program memory 24 bit words, and the BWCOUNT register is set to 32. This causes 32 words of on-chip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to load in the remaining program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at address 0. The ADSP-2100 Family Development Software (Revision 5.02 and later) fully supports the BDMA booting feature and can generate byte memory space compatible boot code. The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. IDMA Booting The ADSP-2183 can also boot programs through its Internal DMA port. If BMODE = 1 and MMAP = 0, the ADSP-2183 boots from the IDMA port. IDMA feature can load as much onchip memory as desired. Program execution is held off until onchip program memory location 0 is written to. The ADSP-2100 Family Development Software (Revision 5.02 and later) can generate IDMA compatible boot code. Bus Request and Bus Grant The ADSP-2183 has two mechanisms to allow automatic loading of the on-chip program memory after reset. The method for booting after reset is controlled by the MMAP and BMODE pins as shown in Table VI. The ADSP-2183 can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal. If the ADSP-2183 is not performing an external memory access, then it responds to the active BR input in the following processor cycle by: * three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, * asserting the bus grant (BG) signal, and * halting program execution. REV. C -9- ADSP-2183 If Go Mode is enabled, the ADSP-2183 will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2183 is performing an external memory access when the external device asserts the BR signal, then it will not three-state the memory interfaces or assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, reenables the output drivers and continues program execution from the point where it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when the ADSP-2183 is ready to execute an instruction, but is stopped because the external bus is already granted to another device. The other device can release the bus by deasserting bus request. Once the bus is released, the ADSP-2183 deasserts BG and BGH and executes the external memory access. Flag I/O Pins * The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP2183's interrupt vector and reset vector map. * Sixteen condition codes are available. For conditional jump, call, return or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. * Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM The ADSP-2183 has on-chip emulation support and an ICEPort, a special set of pins that interface to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE's in-circuit probe, a 14-pin plug. The ICE-Port interface consists of the following ADSP-2183 pins: EBR EMS ELIN EBG EINT ELOUT ERESET ECLK EE The ADSP-2183 has eight general purpose programmable input/output flag pins. They are controlled by two memory mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP-2183's clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset. In addition to the programmable flags, the ADSP-2183 has five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and FL2. FL0-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT are available as an alternate configuration of SPORT1. INSTRUCTION SET DESCRIPTION These ADSP-2183 pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pulldown resistors. The traces for these signals between the ADSP2183 and the connector must be kept as short as possible, no longer than three inches. The following pins are also used by the EZ-ICE: BR RESET BG GND The ADSP-2183 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor's unique architecture, offers the following benefits: * The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation. * Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-2183 in the target system. This causes the processor to use its ERESET, EBR and EBG pins instead of the RESET, BR and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system. The EZ-ICE connects to your target system via a ribbon cable and a 14-pin female plug. The ribbon cable is 10 inches in length with one end fixed to the EZ-ICE. The female plug is plugged onto the 14-pin connector (a pin strip header) on the target board. -10- REV. C ADSP-2183 Target Board Connector for EZ-ICE Probe The EZ-ICE connector (a standard pin strip header) is shown in Figure 7. You must add this connector to your target board design if you intend to use the EZ-ICE. Be sure to allow enough room in your system to fit the EZ-ICE probe onto the 14-pin connector. 1 GND 3 EBG 2 BG 4 BR 6 EINT Restriction: All memory strobe signals on the ADSP-2183 (RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your target system must have 10 k pull-up resistors connected when the EZ-ICE is being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These resistors may be removed at your option when the EZ-ICE is not being used. Target System Interface Signals 5 EBR When the EZ-ICE board is installed, the performance on some system signals changes. Design your system to be compatible with the following system interface signal changes introduced by the EZ-ICE board: * EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the RESET signal. * EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the BR signal. * EZ-ICE emulation ignores RESET and BR when singlestepping. * EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted). * EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target system may take control of the DSP's external memory bus only if bus grant (BG) is asserted by the EZ-ICE board's DSP. Target Architecture File 7 KEY (NO PIN) 9 ELOUT 8 ELIN 10 ECLK 11 EE 12 EMS 13 RESET 14 ERESET TOP VIEW Figure 7. Target Board Connector for EZ-ICE The 14-pin, 2-row pin strip header is keyed at the Pin 7 location--you must remove Pin 7 from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 x 0.1 inches. The pin strip header must have at least 0.15 inch clearance on all sides to accept the EZ-ICE probe plug. Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec. Target Memory Interface For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed below. PM, DM, BM, IOM and CM The EZ-ICE software lets you load your program in its linked (executable) form. The EZ-ICE PC program can not load sections of your executable located in boot pages (by the linker). With the exception of boot page 0 (loaded into PM RAM), all sections of your executable mapped into boot pages are not loaded. Write your target architecture file to indicate that only PM RAM is available for program storage, when using the EZ-ICE software's loading feature. Data can be loaded to PM RAM or DM RAM. Design your Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM), and Composite Memory (CM) external interfaces to comply with worst case device timing requirements and switching characteristics as specified in the DSP's data sheet. The performance of the EZ-ICE may approach published worst case specification for some memory access timing requirements and switching characteristics. Note: If your target does not meet the worst case chip specification for memory access parameters, you may not be able to emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may have trouble manufacturing your system as DSP components statistically vary in switching characteristic and timing requirements within published limits. REV. C -11- ADSP-2183-SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade Parameter VDD TAMB Supply Voltage Ambient Operating Temperature Min 3.0 0 Max 3.6 +70 Min 3.0 -40 B Grade Max 3.6 +85 Unit V C ELECTRICAL CHARACTERISTICS Parameter VIH VIL VOH Hi-Level Input Voltage1, 2 Lo-Level Input Voltage1, 3 Hi-Level Output Voltage1, 4, 5 Test Conditions @ VDD = max @ VDD = min @ VDD = min IOH = -0.5 mA @ VDD = min IOH = -100 A6 @ VDD = min IOL = 2 mA @ VDD = max VIN = VDD max @ VDD = max VIN = 0 V @ VDD = max VIN = VDD max8 @ VDD = max VIN = 0 V8 @ VDD = 3.3 TAMB = +25C tCK = 19 ns11 tCK = 25 ns11 tCK = 30 ns11 tCK = 34.7 ns11 @ VDD = 3.3 TAMB = +25C tCK = 19 ns11 tCK = 25 ns11 tCK = 30 ns11 tCK = 34.7 ns11 @ VIN = 2.5 V fIN = 1.0 MHz TAMB = +25C @ VIN = 2.5 V fIN = 1.0 MHz TAMB = +25C Min 2.0 0.4 2.4 VDD - 0.3 0.4 10 10 10 8 K/B Grades Typ Max Unit V V V V V A A A A mA mA mA mA VOL IIH IIL IOZH IOZL IDD Lo-Level Output Voltage1, 4, 5 Hi-Level Input Current3 Lo-Level Input Current3 Three-State Leakage Current7 Three-State Leakage Current7 Supply Current (Idle)9, 10 10 9 8 6 IDD Supply Current (Dynamic)10, 12 44 35 30 26 mA mA mA mA CI CO Input Pin Capacitance3, 6, 13 Output Pin Capacitance6, 7, 13, 14 8 pF 8 pF NOTES 1 Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD0-IAD15, PF0-PF7. 12 Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL. 13 Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, IS, IAL, IRD, IWR, IRQL0, IRQL1, IRQE, PWD. 14 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, IACK, PWDACK, A0-A13, DT0, DT1, CLKOUT, FL2-0. 15 Although specified for TTL outputs, all ADSP-2183 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads. 16 Guaranteed but not tested. 17 Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, IAD0-IAD15, PF0-PF7. 18 0 V on BR, CLKIN Active (to force three-state condition). 19 Idle refers to ADSP-2183 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND. 10 Current reflects device operating with no output loads. 11 VIN = 0.4 V and 2.4 V. For typical figures for supply currents, refer to Power Dissipation section. 12 IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are 1 type 2 and type 6, and 20% are idle instructions. 13 Applies to LQFP package type and Mini-BGA. 14 Output pin capacitance is the capacitive load for any three-stated output pin. Specifications subject to change without notice. -12- REV. C ADSP-2183 ABSOLUTE MAXIMUM RATINGS * Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +4.6 V Input Voltage . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Output Voltage Swing . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Operating Temperature Range (Ambient) . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . . +280C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD SENSITIVITY ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2183 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE TIMING PARAMETERS GENERAL NOTES MEMORY TIMING SPECIFICATIONS Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add up parameters to derive longer times. TIMING NOTES The table below shows common memory device specifications and the corresponding ADSP-2183 timing parameters, for your convenience. Memory Device Specification ADSP-2183 Timing Timing Parameter Parameter Definition A0-A13, xMS Setup before WR Low A0-A13, xMS Setup before WR Deasserted A0-A13, xMS Hold after WR Deasserted Data Setup before WR High Data Hold after WR High RD Low to Data Valid A0-A13, xMS to Data Valid Switching Characteristics specify how the processor changes its signals. You have no control over this timing--circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. Address Setup to tASW Write Start Address Setup to tAW Write End Address Hold Time tWRA Data Setup Time tDW Data Hold Time tDH OE to Data Valid tRDD Address Access Time tAA xMS = PMS, DMS, BMS, CMS, IOMS. FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS tCK is defined as 0.5tCKI. The ADSP-2183 uses an input clock with a frequency equal to half the instruction rate: a 16.67 MHz input clock (which is equivalent to 60 ns) yields a 30 ns processor cycle (equivalent to 33 MHz). tCK values within the range of 0.5tCKI period should be substituted for all relevant timing parameters to obtain the specification value. Example: tCKH = 0.5tCK - 7 ns = 0.5 (34.7 ns) - 7 ns = 10.35 ns REV. C -13- ADSP-2183 Parameter Clock Signals and Reset Timing Requirements: tCKI CLKIN Period CLKIN Width Low tCKIL tCKIH CLKIN Width High Switching Characteristics: CLKOUT Width Low tCKL tCKH CLKOUT Width High tCKOH CLKIN High to CLKOUT High Control Signals Timing Requirement: tRSP RESET Width Low Min Max Unit 38 15 15 0.5tCK - 7 0.5tCK - 7 0 100 ns ns ns ns ns ns 20 5tCK1 ns NOTE 1 Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). tCKI tCKIH CLKIN tCKIL tCKOH tCKH CLKOUT tCKL Figure 8. Clock Signals Parameter Interrupts and Flag Timing Requirements: IRQx, FI, or PFx Setup before CLKOUT Low 1, 2, 3, 4 tIFS tIFH IRQx, FI, or PFx Hold after CLKOUT High 1, 2, 3, 4 Switching Characteristics: Flag Output Hold after CLKOUT Low5 tFOH tFOD Flag Output Delay from CLKOUT Low5 Min Max Unit 0.25tCK + 15 0.25tCK 0.5tCK - 7 0.5tCK + 6 ns ns ns ns NOTES 1 If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User's Manual for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE. 4 PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7. 5 Flag outputs = PFx, FL0, FL1, FL2, Flag_out4. tFOD CLKOUT tFOH FLAG OUTPUTS tIFH IRQx FI PFx tIFS Figure 9. Interrupts and Flags -14- REV. C ADSP-2183 Parameter Bus Request-Bus Grant Timing Requirements: BR Hold after CLKOUT High1 tBH BR Setup before CLKOUT Low1 tBS Switching Characteristics: tSD CLKOUT High to xMS, RD, WR Disable xMS, RD, WR tSDB Disable to BG Low BG High to xMS, tSE RD, WR Enable tSEC xMS, RD, WR Enable to CLKOUT High tSDBH xMS, RD, WR Disable to BGH Low2 BGH High to xMS, tSEH RD, WR Enable2 0.25tCK + 2 0.25tCK + 17 0.25tCK + 10 0 0 0.25tCK - 4 0 0 ns ns ns Min Max Unit ns ns ns ns ns NOTES xMS = PMS, DMS, CMS, IOMS, BMS. 1 BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User's Manual, Third Edition, for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor requires control of the bus to continue. tBH CLKOUT BR tBS CLKOUT PMS, DMS BMS, RD WR BG tSD tSEC tSDB BGH tSE tSDBH tSEH Figure 10. Bus Request-Bus Grant REV. C -15- ADSP-2183 Parameter Memory Read Timing Requirements: RD Low to Data Valid tRDD A0-A13, xMS to Data Valid tAA tRDH Data Hold from RD High Switching Characteristics: RD Pulsewidth tRP tCRD CLKOUT High to RD Low A0-A13, xMS Setup before RD Low tASR A0-A13, xMS Hold after RD Deasserted tRDA tRWR RD High to RD or WR Low w = wait states x tCK. xMS = PMS, DMS, CMS, IOMS, BMS. Min Max Unit 0.5tCK - 8 + w 0.75tCK - 10.5 + w 0 0.5tCK - 5 + w 0.25tCK - 2 0.25tCK - 4 0.25tCK - 3 0.5tCK - 5 ns ns ns ns ns ns ns ns 0.25tCK + 7 CLKOUT A0 - A13 DMS, PMS, BMS, IOMS, CMS tRDA RD tASR tCRD D tRP tRWR tAA WR tRDD tRDH Figure 11. Memory Read -16- REV. C ADSP-2183 Parameter Memory Write Switching Characteristics: Data Setup before WR High tDW Data Hold after WR High tDH tWP WR Pulsewidth tWDE WR Low to Data Enabled A0-A13, xMS Setup before WR Low tASW tDDR Data Disable before WR or RD Low tCWR CLKOUT High to WR Low A0-A13, xMS, Setup before WR Deasserted tAW tWRA A0-A13, xMS Hold after WR Deasserted tWWR WR High to RD or WR Low w = wait states x tCK. xMS = PMS, DMS, CMS, IOMS, BMS. Min Max Unit 0.5tCK - 7 + w 0.25tCK - 2 0.5tCK - 5 + w 0 0.25tCK - 4 0.25tCK - 4 0.25tCK - 2 0.75tCK - 9 + w 0.25tCK - 3 0.5tCK - 5 0.25 tCK + 7 ns ns ns ns ns ns ns ns ns ns CLKOUT A0-A13 DMS, PMS, BMS, CMS, IOMS WR tWRA tASW tAW tCWR D tWP tDH tWWR tDDR tWDE RD tDW Figure 12. Memory Write REV. C -17- ADSP-2183 Parameter Serial Ports Timing Requirements: SCLK Period tSCK tSCS DR/TFS/RFS Setup before SCLK Low DR/TFS/RFS Hold after SCLK Low tSCH SCLKIN Width tSCP Switching Characteristics: CLKOUT High to SCLKOUT tCC SCLK High to DT Enable tSCDE tSCDV SCLK High to DT Valid TFS/RFSOUT Hold after SCLK High tRH TFS/RFSOUT Delay from SCLK High tRD tSCDH DT Hold after SCLK High TFS (Alt) to DT Enable tTDE TFS (Alt) to DT Valid tTDV tSCDD SCLK High to DT Disable tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid 38 4 7 15 0.25tCK 0 0 15 0 0 14 15 15 0.25tCK + 10 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min Max Unit CLKOUT tCC tCC tSCP tSCS tSCH tSCK SCLK tSCP DR TFSIN RFSIN tRD tRH RFSOUT TFSOUT tSCDD tSCDV tSCDE tSCDH DT tTDE tTDV TFS ALTERNATE FRAME MODE tRDV RFS MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) Figure 13. Serial Ports -18- REV. C ADSP-2183 Parameter IDMA Address Latch Timing Requirements: Duration of Address Latch1, 2 tIALP IAD15-0 Address Setup before Address Latch End2 tIASU tIAH IAD15-0 Address Hold after Address Latch End2 tIKA IACK Low before Start of Address Latch1 tIALS Start of Write or Read after Address Latch End2, 3 NOTES 1 Start of Address Latch = IS Low and IAL High. 2 End of Address Latch = IS High or IAL Low. 3 Start of Write or Read = IS Low and IWR Low or IRD Low. Min Max Unit 10 5 2 0 3 ns ns ns ns ns IACK tIKA IAL tIALP IS tIASU IAD15-0 tIAH tIALS IRD OR IWR Figure 14. IDMA Address Latch REV. C -19- ADSP-2183 Parameter IDMA Write, Short Write Cycle Timing Requirements: IACK Low before Start of Write1 tIKW Duration of Write1, 2 tIWP tIDSU IAD15-0 Data Setup before End of Write2, 3, 4 tIDH IAD15-0 Data Hold after End of Write2, 3, 4 Switching Characteristic: tIKHW Start of Write to IACK High NOTES 1 Start of Write = IS Low and IWR Low. 2 End of Write = IS High or IWR High. 3 If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH. 4 If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH. tIKW IACK Min Max Unit 0 15 5 2 15 ns ns ns ns ns tIKHW IS tIWP IWR tIDSU IAD15-0 DATA tIDH Figure 15. IDMA Write, Short Write Cycle -20- REV. C ADSP-2183 Parameter IDMA Write, Long Write Cycle Timing Requirements: IACK Low before Start of Write1 tIKW IAD15-0 Data Setup before IACK Low2, 3 tIKSU tIKH IAD15-0 Data Hold after IACK Low2, 3 Switching Characteristics: Start of Write to IACK Low4 tIKLW tIKHW Start of Write to IACK High 0 0.5tCK + 10 2 1.5tCK 15 ns ns ns ns ns Min Max Unit NOTES 1 Start of Write = IS Low and IWR Low. 2 If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH. 3 If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH. 4 This is the earliest time for IACK Low from Start of Write. For IDMA Write Cycle relationships, please refer to the ADSP-21xx Family User's Manual, Third Edition. tIKW IACK tIKHW tIKLW IS IWR tIKSU IAD15-0 DATA tIKH Figure 16. IDMA Write, Long Write Cycle REV. C -21- ADSP-2183 Parameter IDMA Read, Long Read Cycle Timing Requirements: IACK Low before Start of Read1 tIKR tIRP Duration of Read Switching Characteristics: IACK High after Start of Read1 tIKHR tIKDS IAD15-0 Data Setup before IACK Low tIKDH IAD15-0 Data Hold after End of Read2 IAD15-0 Data Disabled after End of Read2 tIKDD tIRDE IAD15-0 Previous Data Enabled after Start of Read tIRDV IAD15-0 Previous Data Valid after Start of Read IAD15-0 Previous Data Hold after Start of Read (DM/PM1)3 tIRDH1 tIRDH2 IAD15-0 Previous Data Hold after Start of Read (PM2)4 NOTES 1 Start of Read = IS Low and IRD Low. 2 End of Read = IS High or IRD High. 3 DM read or first half of PM read. 4 Second half of PM read. Min Max Unit 0 15 15 0.5tCK - 7 0 10 0 15 2tCK - 5 tCK - 5 ns ns ns ns ns ns ns ns ns ns IACK tIKR IS tIKHR tIRP IRD tIRDE IAD15-0 PREVIOUS DATA tIKDS READ DATA tIKDH tIRDV tIRDH tIKDD Figure 17. IDMA Read, Long Read Cycle -22- REV. C ADSP-2183 Parameter IDMA Read, Short Read Cycle Timing Requirements: IACK Low before Start of Read1 tIKR Duration of Read tIRP Switching Characteristics: tIKHR IACK High after Start of Read1 IAD15-0 Data Hold after End of Read2 tIKDH tIKDD IAD15-0 Data Disabled after End of Read2 tIRDE IAD15-0 Previous Data Enabled after Start of Read tIRDV IAD15-0 Previous Data Valid after Start of Read NOTES 1 Start of Read = IS Low and IRD Low. 2 End of Read = IS High or IRD High. Min Max Unit 0 15 15 0 10 0 15 ns ns ns ns ns ns ns IACK tIKR tIKHR IS IRD tIRP tIRDE tIKDH PREVIOUS DATA IAD15-0 tIRDV tIKDD Figure 18. IDMA Read, Short Read Cycle REV. C -23- ADSP-2183 OUTPUT DRIVE CURRENTS Figure 19 shows typical I-V characteristics for the output drivers of the ADSP-2183. The curves represent the current drive capability of the output drivers as a function of output voltage. 100 75 50 PINT = internal power dissipation from Power vs. Frequency graph (Figure 20). (C x VDD2 x f ) is calculated for each output: # of Pins x C x VDD2 x 3.3 V x 3.32 V x 3.32 V x 3.32 V 2 xf x 33.3 MHz x 16.67 MHz x 16.67 MHz x 33.3 MHz = 29.0 mW = 16.3 mW = 1.8 mW = 3.6 mW 50.7 mW SOURCE CURRENT - mA 25 0 -25 -50 -75 -100 -125 -150 -175 -200 0 3.6V, -40C 3.3V, +25C 3.0V, +85C Address, DMS Data Output, WR RD CLKOUT 8 9 1 1 x 10 pF x 10 pF x 10 pF x 10 pF 3.0V, +85C 3.3V, +25C Total power dissipation for this example is PINT + 50.7 mW. 3.6V, -40C 220 205 190 184mW VDD = 3.6V 150mW VDD = 3.3V 120mW VDD = 3.0V 2183 POWER, INTERNAL1, 3, 4 0.75 1.50 2.25 3.00 3.75 SOURCE VOLTAGE - V 4.50 5.25 175 160 145 130 115 100 90mW 110mW Figure 19. Typical Drive Currents 1000 CURRENT (LOG SCALE) - A 100 VDD = 3.6V VDD = 3.3V VDD = 3.0V 85 72mW 70 28 32 36 40 44 1/tCK - MHz 48 52 50 10 POWER, IDLE1, 2, 3 45 40 35 30 27mW 25 VDD = 3.6V 30mW VDD = 3.3V 24mW VDD = 3.0V 15mW 38mW 0 0 25 55 TEMPERATURE - C 85 20mW 20 15 10 5 0 28 32 36 40 44 1/tCK - MHz NOTES: 1. REFLECTS ADSP-2183 OPERATION IN LOWEST POWER MODE. (SEE "SYSTEM INTERFACE" CHAPTER OF THE ADSP-2100 FAMILY USER'S MANUAL FOR DETAILS.) 2. CURRENT REFLECTS DEVICE OPERATING WITH NO INPUT LOADS. Figure 20. Power-Down Supply Current (Typical) POWER DISSIPATION 48 52 32 30 28 26 24 22 20 18 16 14 12 10 8 11mW 20mW POWER, IDLE n MODES3 30mW IDLE To determine total power dissipation in a specific application, the following equation should be applied for each output: C x VDD2 x f C = load capacitance, f = output switching frequency. Example: In an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: Assumptions: 13.8mW IDLE (16) IDLE (128) 13mW 10.6mW 28 32 36 40 44 1/tCK - MHz 48 52 * * * * External data memory is accessed every cycle with 50% of the address pins switching. External data memory writes occur every other cycle with 50% of the data pins switching. Each address and data pin has a 10 pF total load at the pin. The application operates at VDD = 3.3 V and tCK = 30.0 ns. Total Power Dissipation = PINT + (C x VDD2 x f ) -24- VALID FOR ALL TEMPERATURE GRADES. 1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2IDLE REFERS TO ADSP-2183 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND. 3TYPICAL POWER DISSIPATION AT 3.3V V DD AND 25 C EXCEPT WHERE SPECIFIED. 4I DD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1,4,5,12,13,14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. Figure 21. Power vs. Frequency REV. C ADSP-2183 CAPACITIVE LOADING Figures 22 and 23 show the capacitive loading characteristics of the ADSP-2183. 25 T = +85 C VDD = 3.0V 20 is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. INPUT OR OUTPUT 1.5V 1.5V RISE TIME (0.4V - 2.4V) - ns Figure 24. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) 15 Output Enable Time 10 5 0 0 20 40 60 80 100 120 CL - pF 140 160 180 200 Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. REFERENCE SIGNAL Figure 22. Typical Output Rise Time vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature) 18 16 14 VALID OUTPUT DELAY OR HOLD - ns tMEASURED tENA VOH (MEASURED) OUTPUT VOL (MEASURED) tDIS VOH (MEASURED) - 0.5V VOL (MEASURED) +0.5V 2.0V 1.0V VOH (MEASURED) 12 10 8 6 4 2 tDECAY OUTPUT STOPS DRIVING VOL (MEASURED) OUTPUT STARTS DRIVING NOMINAL -2 -4 -6 0 40 80 120 CL - pF 160 200 HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V. Figure 25. Output Enable/Disable IOL Figure 23. Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature) TEST CONDITIONS Output Disable Time TO OUTPUT PIN +1.5V 50pF Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference of tMEASURED and tDECAY, as shown in the Output Enable/Disable diagram. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. The decay time, tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the following equation: t DECAY = CL * 0.5V iL IOH Figure 26. Equivalent Device Loading for AC Measurements (Including All Fixtures) ENVIRONMENTAL CONDITIONS Ambient Temperature Rating: TAMB = TCASE - (PD x CA) TCASE = Case Temperature in C PD = Power Dissipation in W CA = Thermal Resistance (Case-to-Ambient) JA = Thermal Resistance (Junction-to-Ambient) JC = Thermal Resistance (Junction-to-Case) Package LQFP Mini-BGA JA JC CA from which t DIS = t MEASURED - t DECAY 50C/W 70.7C/W 2C/W 7.4C/W 48C/W 63.3C/W REV. C -25- ADSP-2183 128-Lead LQFP Package Pinout 108 IAD12 120 IAD2 118 IAD4 119 IAD3 128 IS 127 GND 105 IAD15 109 IAD11 106 IAD14 110 IAD10 107 IAD13 122 IAD0 121 IAD1 117 IAD5 113 IAD7 112 IAD8 116 GND 114 IAD6 111 IAD9 104 IRD 103 IWR 102 GND 101 D23 100 D22 99 D21 98 D20 97 D19 96 D18 95 D17 94 D16 93 D15 92 GND 91 VDD 90 GND 89 D14 88 D13 87 D12 86 D11 85 D10 84 D9 83 D8 82 D7 81 D6 80 D5 79 GND 78 D4 77 D3 76 D2 75 D1 74 D0 73 VDD 72 BG 71 EBG 70 BR 69 EBR 68 EINT 67 ELIN 66 ELOUT 65 ECLK 126 PF4 IAL PF3 PF2 PF1 PF0 WR RD IOMS BMS 1 2 3 4 5 6 7 8 9 PIN 1 IDENTIFIER DMS 10 CMS 11 GND 12 VDD 13 PMS 14 A0 15 A1 16 A2 17 A3 18 A4 19 A5 20 A6 21 A7 22 XTAL 23 CLKIN 24 GND 25 CLKOUT 26 GND 27 VDD 28 A8 29 A9 30 A10 31 A11 32 A12 33 A13 34 IRQE 35 MMAP 36 PWD 37 IRQ2 38 123 PF7 124 PF6 125 PF5 ADSP-2183 TOP VIEW (Not to Scale) 115 VDD BMODE 39 TFS0 51 -26- TFS1/ IRQ1 56 RFS1/IRQ0 57 GND 58 PWDACK 40 ERESET 61 RESET 62 DR1/FI 59 DT1/F0 55 SCLK1 60 IRQL0 45 IRQL1 46 IACK 41 BGH 42 SCLK0 54 GND 44 RFS0 52 EMS 63 EE 64 VDD 43 FL0 47 DR0 53 DT0 50 FL1 48 FL2 49 REV. C ADSP-2183 LQFP Pin Configurations LQFP Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name IAL PF3 PF2 PF1 PF0 WR RD IOMS BMS DMS CMS GND VDD PMS A0 A1 A2 A3 A4 A5 A6 A7 XTAL CLKIN GND CLKOUT GND VDD A8 A9 A10 A11 LQFP Number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name A12 A13 IRQE MMAP PWD IRQ2 BMODE PWDACK IACK BGH VDD GND IRQL0 IRQL1 FL0 FL1 FL2 DT0 TFS0 RFS0 DR0 SCLK0 DT1/F0 TFS1/IRQ1 RFS1/IRQ0 GND DR1/FI SCLK1 ERESET RESET EMS EE LQFP Number 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Pin Name ECLK ELOUT ELIN EINT EBR BR EBG BG VDD D0 D1 D2 D3 D4 GND D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 GND VDD GND D15 D16 D17 D18 LQFP Number 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Pin Name D19 D20 D21 D22 D23 GND IWR IRD IAD15 IAD14 IAD13 IAD12 IAD11 IAD10 IAD9 IAD8 IAD7 IAD6 VDD GND IAD5 IAD4 IAD3 IAD2 IAD1 IAD0 PF7 PF6 PF5 PF4 GND IS REV. C -27- ADSP-2183 144-Lead Mini-BGA Package Pinout (Bottom View) 12 11 10 9 8 7 6 5 4 3 2 1 GND GND IWR IAD14 IAD10 IAD6 GND IAD2 PF6 GND IS IAL A D21 D23 IRD IAD15 IAD11 VDD GND IAD1 PF5 GND PF3 PF1 B D17 D20 D22 IAD13 IAD8 VDD IAD0 PF4 PF2 WR PF0 RD C GND D15 D18 D19 D16 IAD9 IAD5 PF7 IOMS GND DMS GND D D14 GND VDD GND GND IAD7 CMS IAD3 BMS A0 VDD VDD E D10 D11 D13 D12 IAD12 D8 IAD4 PMS A3 A4 A1 A2 F D6 D5 D9 D4 D7 DT0 A7 A8 A6 GND A5 XTAL G GND D2 GND D0 D3 DT1 IRQL0 VDD GND GND GND CLKIN H VDD VDD D1 BG RFS1 SCLK0 IRQL1 VDD VDD A10 VDD CLKOUT J EBG BR EBR ERESET SCLK1 TFS1 TFS0 FL2 PWDACK A11 A12 A9 K EINT ELOUT ELIN RESET GND DR0 FL0 GND IACK IRQE MMAP A13 L ECLK EE EMS DR1 GND RFS0 FL1 GND BGH BMODE IRQ2 PWD M -28- REV. C ADSP-2183 Mini-BGA Pin Configurations Ball # A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 Name IAL IS GND PF6 IAD2 GND IAD6 IAD10 IAD14 IWR GND GND PF1 PF3 GND PF5 IAD1 GND VDD IAD11 IAD15 IRD D23 D21 RD PF0 WR PF2 PF4 IAD0 VDD IAD8 IAD13 D22 D20 D17 Ball # D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 Name GND DMS GND IOMS PF7 IAD5 IAD9 D16 D19 D18 D15 GND VDD VDD A0 BMS IAD3 CMS IAD7 GND GND VDD GND D14 A2 A1 A4 A3 PMS IAD4 D8 IAD12 D12 D13 D11 D10 Ball # G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 Name XTAL A5 GND A6 A8 A7 DT0 D7 D4 D9 D5 D6 CLKIN GND GND GND VDD IRQL0 DT1 D3 D0 GND D2 GND CLKOUT VDD A10 VDD VDD IRQL1 SCLK0 RFS1 BG D1 VDD VDD Ball # K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 Name A9 A12 A11 PWDACK FL2 TFS0 TFS1 SCLK1 ERESET EBR BR EBG A13 MMAP IRQE IACK GND FL0 DR0 GND RESET ELIN ELOUT EINT PWD IRQ2 BMODE BGH GND FL1 RFS0 GND DR1 EMS EE ECLK REV. C -29- ADSP-2183 OUTLINE DIMENSIONS Dimensions given in mm and (inches). 128-Lead Metric Plastic Thin Quad Flatpack (LQFP) (ST-128) 16.20 (0.638) 16.00 (0.630) 15.80 (0.622) 1.60 (0.063) MAX 0.75 (0.030) 0.60 (0.024) 0.50 (0.020) SEATING PLANE 128 1 103 102 TOP VIEW 20.10 (0.792) 20.00 (0.787) 19.90 (0.783) 65 64 (PINS DOWN) 0.08 (0.003) MAX LEAD COPLANARITY 0.15 (0.006) 0.05 (0.002) 1.45 (0.057) 1.40 (0.055) 1.35 (0.053) 38 39 0.50 (0.020) BSC LEAD PITCH 0.27 (0.011) 0.22 (0.009) 0.17 (0.007) LEAD WIDTH 14.10 (0.555) 14.00 (0.551) 13.90 (0.547) NOTES: THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 (0.0032) FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED -30- 22.20 (0.874) 22.00 (0.866) 21.80 (0.858) REV. C ADSP-2183 OUTLINE DIMENSIONS Dimensions given in mm and (inches). 144-Lead Mini-BGA Package Pinout (CA-144) 0.404 (10.25) 0.394 (10.00) SQ 0.384 (9.75) 12 11 10 9 8 7 6 5 4 3 2 1 TOP VIEW 0.404 (10.25) 0.394 (10.00) SQ 0.384 (9.75) 0.346 (8.80) BSC 0.031 (0.80) BSC A B C D E F G H J K L M DETAIL A 0.067 (1.70) MAX 0.010 (0.25) NOM NOTE THE ACTUAL POSITION OF THE BALL POPULATION 0.010 (0.25) MIN IS WITHIN 0.006 (0.150) OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.003 (0.08) OF ITS IDEAL POSITION RELATIVE TO THE BALL POPULATION. 0.031 (0.80) BSC 0.346 (8.80) BSC DETAIL A 0.034 (0.85) MIN 0.022 (0.55) 0.005 (0.12) 0.020 (0.50) MAX 0.018 (0.45) BALL DIAMETER SEATING PLANE ORDERING GUIDE Part Number ADSP-2183KST-115 ADSP-2183BST-115 ADSP-2183KST-133 ADSP-2183BST-133 ADSP-2183KST-160 ADSP-2183BST-160 ADSP-2183KST-210 ADSP-2183KCA-210 Ambient Temperature Range 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C 0C to +70C Instruction Rate (MHz) 28.8 28.8 33.3 33.3 40 40 52 52 Package Description 128-Lead LQFP 128-Lead LQFP 128-Lead LQFP 128-Lead LQFP 128-Lead LQFP 128-Lead LQFP 128-Lead LQFP 144-Lead Mini-BGA Package Option ST-128 ST-128 ST-128 ST-128 ST-128 ST-128 ST-128 CA-144 REV. C -31- PRINTED IN U.S.A. C00184b-0-7/00 (rev. C) |
Price & Availability of ADSP-2183BST-115
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |